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rt8816a ? DS8816A-00 september 2016 www.richtek.com 1 copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? dual-phase pwm controller with pwm-vid reference general description the rt8816a is a 2/1 phase synchronous buck pwm controller which is optimized for high performance graphic microprocessor and computer applications. the ic integrates a constant-on-time (cot) pwm controller, two mosfet drivers with internal bootstrap diodes, as well as channel current balance and protection functions including over-voltage protection (ovp), under-voltage protection (uvp), current limit, and thermal shutdown into the wqfn-20l 3x3 package. the rt8816a adopts r ds(on) current sensing technique. current limit is accomplished through continuous inductor- current-sense, while r ds(on) current sensing is used for accurate channel current balance. using the method of current sampling utilizes the best advantages of each technique. the rt8816a features external reference input and pwm- vid dynamic output voltage control, in which the feedback voltage is regulated and tracks external input reference voltage. other features include adjustable switching frequency, dynamic phase number control, internal soft- start, power good indicator, and enable functions. features ? ? ? ? ? dual-phase pwm controller ? ? ? ? ? power state indicator ? ? ? ? ? 1p-ccm/2p-ccm/1p-dem/2p-dem ? ? ? ? ? two embedded mosfet drivers and embedded switching boot diode ? ? ? ? ? support 1.8v pwm-vid interface ? ? ? ? ? external reference input control ? ? ? ? ? pwm-vid dynamic voltage control ? ? ? ? ? dynamic phase number control ? ? ? ? ? lossless r ds(on) current sensing for current balance ? ? ? ? ? internal/external soft-start ? ? ? ? ? adjustable current limit threshold ? ? ? ? ? adjustable switching frequency ? ? ? ? ? uvp/ovp protection ? ? ? ? ? shoot through protection and short pulse free technology ? ? ? ? ? support an ultra-low output voltage as standby voltage ? ? ? ? ? thermal shutdown ? ? ? ? ? power good indicator (en to pg high = 500 s) applications ? cpu/gpu core power supply ? desktop pc memory, vtt power ? chipset/ram power supply ? generic dc-dc power regulator ordering information note : richtek products are : ? rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. package type qw : wqfn-20l 3x3 (w-type) lead plating system g : green (halogen free and pb free) rt8816a marking information 7j=ym dnn 7j= : product code ymdnn : date code pin configuration (top view) wqfn-20l 3x3 psi en boot1 ugate1 boot2 ugate2 ocset/ss pgood refadj refin ton phase1 lgate1 lgate2 pvcc 15 14 13 12 17 18 19 20 1 2 3 4 9 8 7 6 gnd 21 11 5 phase2 16 vid vsns rgnd 10 vref
rt8816a 2 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name pin function 1 boot1 bootstrap supply for pwm1. this pin powers the high-side mosfet driver. 2 ugate1 high-side gate driver of pwm1. this pin provides the gate drive for the converter's high-side mosfet. connect this pin to the gate of high-side mosfet. 3 en enable control input. active high input. when pvcc por, the input voltage must not be over pvcc. 4 psi power saving interface. when the voltage is pulled below 0.4v, the device will operate into 1 phase dem. when the voltage is between 0.7v to 0.88v, the device will operate into 1 phase force ccm. when the voltage is between 1.08v to 1.35v, the device will operate into 2 phase dem. when the voltage is between 1.6v to 5.5v, the device will operate into 2 phase force ccm. 5 vid programming output voltage control input. refer to pwm-vid dynamic voltage control. 6 refadj reference adjustment output. refer to pwm-vid dynamic voltage control. 7 refin external reference input. 8 vref reference voltage output. this is a high precision voltage reference (2v) from the vref pin to rgnd pin. 9 ton on-time/switching frequency adjustment input. connect a 100pf ceramic capacitor between c ton and ground is optional for noise immunity enhancement. 10 rgnd negative remote sense input. connect this pin to the ground of output load. 11 vsns positive remote sense input. connect this pin to the positive terminal of output load. 12 ocset/ss current limit setting. connect a resistor from ocset/ss to gnd to set the current limit threshold. the external soft start time also can be set through by connecting a capacitor from ocset/ss pin to gnd. 13 pgood power good indicator output. active high open-drain output. 14 ugate2 high-side gate driver of pwm2. this pin provides the gate drive for the converter's high-side mosfet. connect this pin to the gate of high-side mosfet. 15 boot2 bootstrap supply for pwm2. this pin powers the high-side mosfet driver. 16 phase2 switch node for pwm2. this pin is return node of the high-side driver of pwm 2. connect this pin to the source of high-side mosfet together with the drain of low-side mosfet and the inductor. 17 lgate2 low-side gate driver of pwm2. this pin provides the gate drive for the converter's low-side mosfet. connect this pin to the gate of low-side mosfet. 18 pvcc supply voltage input. connect this pin to a 5v bias supply. place a high quality bypass capacitor from this pin to gnd. 19 lgate1 low-side gate driver of pwm1. this pin provides the gate drive for the converter's low-side mosfet. connect this pin to the gate of low-side mosfet. 20 phase1 switch node for pwm1. this pin is return node of the high-side driver of pwm 1. connect this pin to the source of high-side mosfet together with the drain of low-side mosfet and the inductor. 21 (exposed pad) gnd ground. the exposed pad should be soldered to a large pcb and connected to gnd for maximum thermal dissipation.
rt8816a 3 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional block diagram lgate2 phase2 ugate2 boot2 lgate1 pvcc phase1 ugate1 boot1 vsns ton refin vref en driver logic boot-phase detection 2 boot-phase detection 1 + - + - s/h s/h current balance control & protection logic ton gen 1 ton gen 2 pwm1 pwm2 to power on reset v in detection to protection logic + - pwm cmp to driver logic to power on reset enable logic + - + - 40% refin power on reset & central logic reference output gen. soft-start & slew rate control uv 150% refin or 2v current limit v b v b pgood vid psi refadj mode select gm gm rgnd ocset/ss ov + - + - x(-1/12) i cs 10 i cs 40 to ssok
rt8816a 4 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation the rt8816a is a dual-phase synchronous buck pwm controller with integrated drivers which are optimized for high performance graphic microprocessor and computer applications. the ic integrates a cot (constant-on-time) pwm controller with two mosfet drivers, as well as output current monitoring and protection functions. referring to the function block diagram of ton genx, the synchronous ugate driver is turned on at the beginning of each cycle. after the internal one-shot timer expires, the ugate driver will be turned off. the pulse width of this one-shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly constant over the input voltage range and output voltage. another one-shot sets a minimum off-time. the rt8816a also features a pwm-vid dynamic voltage control circuit driven by the pulse width modulation method. this circuit reduces the device pin count and enables a wide dynamic voltage range. soft-start (ss) for soft-start function, an internal current source charges an internal capacitor to build the soft-start ramp voltage. the output voltage will track the internal ramp voltage during soft-start interval. pgood the power good output is an open-drain architecture. when the soft-start is finished, the pgood open-drain output will be high impedance. current balance the rt8816a implements internal current balance mechanism in the current loop. the rt8816a senses per phase current and compares it with the average current. if the sensed current of any particular phase is higher than average current, the on-time of this phase will be adjusted to be shorter. current limit the current limit circuit employs a unique ? valley ? current sensing algorithm. if the magnitude of the current sense signal at phase is above the current limit threshold, the pwm is not allowed to initiate a new cycle. thus, the current to the load exceeds average output inductor current, the output voltage falls and eventually crosses the under-voltage protection threshold, inducing ic shutdown. over-voltage protection (ovp) & under-voltage protection (uvp) the output voltage is continuously monitored for over- voltage and under-voltage protection. when the output voltage exceeds its set voltage threshold (if v refin 1.33v, ov = 2v, or v refin > 1.33v, ov = 1.5 x v refin ), ugate goes low and lgate is forced high; when it is less than 40% of its set voltage, under voltage protection is triggered and then both ugate and lgate gate drivers are forced low. the controller is latched until pvcc is re-supplied and exceeds the por rising threshold voltage or en is reset.
rt8816a 5 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. absolute maximum ratings (note 1) ? ton to gnd ------------------------------------------------------------------------------------------------------------------ ? 0.3v to 30v ? rgnd to gnd --------------------------------------------------------------------------------------------------------------- ? 0.7v to 0.7v ? bootx to phasex -------------------------------------------------------------------------------------------------------- ? 0.3v to 6v ? bootx to gnd ------------------------------------------------------------------------------------------------------------- ? 0.3v to 36v ? phasex to gnd dc -------------------------------------------------------------------------------------------------------------------------- ---- ? 0.3v to 30v <20ns ----------------------------------------------------------------------------------------------------------------------- -- ? 8v to 36v ? ugatex to phasex dc -------------------------------------------------------------------------------------------------------------------------- ---- ? 0.3v to 6v <20ns ----------------------------------------------------------------------------------------------------------------------- -- ? 5v to 7.5v ? lgatex to gnd dc -------------------------------------------------------------------------------------------------------------------------- ---- ? 0.3v to 6v <20ns ----------------------------------------------------------------------------------------------------------------------- -- ? 2.5v to 7.5v ? other pins -------------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v ? power dissipation, p d @ t a = 25 c wqfn-20l 3x3 ------------------------------------------------------------------------------------------------------------- 3.33w ? package thermal resistance (note 2) wqfn-20l 3x3, ja -------------------------------------------------------------------------------------------------------- 30 c/w wqfn-20l 3x3, jc ------------------------------------------------------------------------------------------------------- 7.5 c/w ? lead temperature (soldering, 10 sec.) -------------------------------------------------------------------------------- 260 c ? junction temperature ------------------------------------------------------------------------------------------------------ 150 c ? storage temperature range --------------------------------------------------------------------------------------------- ? 65 c to 150 c ? esd susceptibility (note 3) hbm (human body model) ----------------------------------------------------------------------------------------------- 1.5kv recommended operating conditions (note 4) ? input voltage, vin ---------------------------------------------------------------------------------------------------------- 2.5 v to 26v ? supply voltage, pvcc ---------------------------------------------------------------------------------------------------- 4.5v to 5.5v ? junction temperature range --------------------------------------------------------------------------------------------- ? 40 c to 125 c ? ambient temperature range --------------------------------------------------------------------------------------------- ? 40 c to 85 c electrical characteristics (t a = 25 c unless otherwise specified) parameter symbol test conditions min typ max unit pwm controller pvcc supply voltage v pvcc 4.5 -- 5.5 v pvcc supply current i supply v en = 3.3v, 1phase dem mode, not switching, vref external r = 40k -- 0.4 -- ma pvcc shutdown current i shdn v en = 0v -- -- 10 ? a pvcc por threshold 3.8 4.1 4.4 v por hysteresis -- 0.3 -- v switching frequency f sw r ton = 500k ? (note 5) 270 300 330 khz
rt8816a 6 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit minimum on-time t on(min) -- 70 -- ns minimum off-time t off(min) -- 300 -- ns en input voltage en input voltage logic-high v en_h 1.2 -- 5.5 v logic-low v en_l -- -- 0.55 mode decision 2 phase ccm v psi 1.6 1.8 5.5 v 2 phase dem v psi 1.08 1.2 1.35 v 1 phase ccm v psi 0.7 0.8 0.88 v 1 phase dem v psi -- 0 0.4 v pwm-vid input voltage for 1.8v gpio setting logic h v pwm-vid_h 1.2 -- -- v logic l v pwm-vid_l -- -- 0.6 v protection function zero current crossing threshold ? 8 -- 8 mv current limit setting current i ocset 9 10 11 ? a current limit setting current temperature coefficient i ocset_tc -- 4700 -- ppm/ ? c current limit threshold r ocset = 120k -- 100 -- mv absolute over-voltage protection threshold v ovp, absolute v refin ? 1.33v 1.9 2 2.1 v relative over-voltage protection threshold v ovp, relative v refin > 1.33v 145 150 155 % ov fault delay fb forced above ov threshold -- 5 -- ? s relative under-voltage protection threshold v uvp uvp 35 40 45 % uv fault delay fb forced above uv threshold -- 3 -- ? s thermal shutdown threshold t sd -- 150 -- ? c vout soft-start (pgood blanking time) from v en = high to vout regulation point, v refin = 1v -- 0.5 -- ms error amplifier vsns error comparator threshold (valley) v refin = 1v ? 11 ? 6 ? 1 mv
rt8816a 7 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured under natural convection (still air) at t a = 25 c with the component mounted on a high effective- thermal-conductivity four-layer test board on a jedec 51-7 thermal measurement standard. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. not production tested. test condition is v in = 8v, v out = 1v, i out = 20a using application circuit. parameter symbol test conditions min typ max unit reference reference voltage v vref sourcing current = 1ma, vid no switching 1.98 2 2.02 v driver on-resistance ugate driver source r ugatesr bootx ? phasex forced to 5v -- 2 4 ? ugate driver sink r ugatesk bootx ? phasex forced to 5v -- 1 2 ? lgate driver source r lgatesr lgatex, high state -- 1.5 3 ? lgate driver sink r lgatesk lgatex, low state -- 0.7 1.5 ? dead-time from lgate falling to ugate rising -- 30 -- ns from ugate falling to lgate rising -- 20 -- internal boost diode resistance r boot pvcc to bootx, i boot = 10ma -- 80 -- ?
rt8816a 8 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit figure 1. 2 active phase configuration figure 2. 1 active phase configuration v out 2 20 19 7 6 8 1 5 14 16 1 7 ugate1 ugate2 rt8816a refin refadj boot2 lgate1 phase2 1 boot1 vref phase1 lgate2 v pvcc v out_sns gnd 21 (exposed pad) 11 vsns v gnd_sns 18 pvcc 13 pgood pgood 4 psi psi 5 vid vid 3 en enable v in v in 10 rgnd r standby r ref1 r ref2 r refadj r boot c refin rgnd rgnd rgnd rgnd rgnd v standby c refadj 1 100k 0.1f 20k 2k 2.7nf 20k 5.1k 18k nc 0 nc 0 0 0.1f 10f x 2 0.36h/1.05m ? nc nc 0.1f 0 0 10f x 2 0.36h/1.05m ? 330f/2v x 4 22f x 15 10 10 470f/50v 470f/50v nc nc 1 2 ocset/ss 9 ton v in r ton 500k 2.2 1f c ton optional 2.2f r ocset 10k c ss nc v out 2 20 19 7 6 8 1 5 14 16 1 7 ugate1 ugate2 rt8816a refin refadj boot2 lgate1 phase2 1 boot1 vref phase1 lgate2 v pvcc gnd 21 (exposed pad) 18 pvcc 13 pgood pgood 4 psi psi 5 vid vid 3 en v in r standby r ref1 r ref2 r refadj r boot c refin rgnd rgnd rgnd rgnd rgnd v standby floating v out_sns 11 vsns v gnd_sns 10 rgnd enable c refadj 1 2.2f 100k 0.1f 20k 2k 20k 2.7nf 18k nc 5.1k 0 nc 0 0 0.1f 10f x 2 0.36h/1.05m ? nc nc 470f/50v 22f x 15 330f/2v x 4 10 10 9 ton v in r ton 500k 2.2 1f c ton optional 12 ocset/ss r ocset 10k c ss nc
rt8816a 9 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics efficiency vs. load current 74 76 78 80 82 84 86 88 90 92 94 0.01 0.1 1 10 100 load current (a) efficiecny (%) v psi = 1.2v, v out = 1v v in = 12v v in = 19v v in = 5v inductor valley current vs. load current -5 0 5 10 15 20 25 30 0 102030405060 load current (a) inductor valley current (a ) i l1 i l2 v in = 19v, v pvcc = 5v current limit setting current vs. temperature 5 6 7 8 9 10 11 12 13 14 15 16 -50 -25 0 25 50 75 100 125 temperature (c) current limit setting current ( a ) v pvcc = 5v, no load reference voltage vs. temperature 1.980 1.985 1.990 1.995 2.000 2.005 2.010 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) v pvcc = 5v, no load power on from en time (200 s/div) ugate2 (20v/div) v in = 12v, v pvcc = 5v, i out = 40a v en (5v/div) ugate1 (20v/div) v out (1v/div) power off from en time (200 s/div) ugate1 (20v/div) v in = 12v, v pvcc = 5v, i out = 40a v en (5v/div) ugate2 (20v/div) v out (1v/div)
rt8816a 10 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. power off from vcc time (20ms/div) v out pvcc power on from pvcc time (1ms/div) ugate2 (20v/div) v pvcc (5v/div) ugate1 (20v/div) v out (1v/div) ugate2 (20v/div) v pvcc (5v/div) ugate1 (20v/div) v out (1v/div) v in = 12v, v pvcc = 5v, i out = 40a v in = 12v, v pvcc = 5v, i out = 40a dynamic output voltage control time (50 s/div) ugate1 (20v/div) v refin = 0.6v to 1.2v, i out = 40a ugate2 (20v/div) v out (600mv/div) v refin (600mv/div) dynamic output voltage control time (50 s/div) ugate1 (20v/div) ugate2 (20v/div) v out (600mv/div) v refin (600mv/div) v refin = 1.2v to 0.6v, i out = 40a v refin v out v refin v out load transient response ugate1 (20v/div) i out (20a/div) ugate2 (20v/div) v out (40mv/div) load transient response ugate1 (20v/div) i out (20a/div) ugate2 (20v/div) v out (40mv/div) v in = 12v, v out = 1v v in = 12v, v out = 1v
rt8816a 11 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ovp time (100 s/div) ugate1 (20v/div) v sns (500mv/div) lgate1 (5v/div) current limit and uvp time (100 s/div) ugate1 (20v/div) v in = 12v, v pvcc = 5v lgate1 (5v/div) v in = 12v, v pvcc = 5v, no load v out (500mv/div) i l1 (10a/div)
rt8816a 12 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information the rt8816a is a dual-phase synchronous buck pwm controller with integrated drivers which is optimized for high performance graphic microprocessor and computer applications. a cot (constant-on-time) pwm controller and two mosfet drivers with internal bootstrap diodes are integrated so that the external circuit can be easily designed and the number of component is reduced. the topology solves the poor load transient response timing problems of fixed-frequency mode pwm and avoids the problems caused by widely varying switching frequencies in conventional constant on-time and constant off-time pwm schemes. the ic supports dynamic mode transition function with various operating states, which include single phase with ccm, dual-phase with ccm, single phase with diode emulation mode and dual-phase with diode emulation mode operation. these different operating states make the system efficiency as high as possible. the rt8816a provides a pwm-vid dynamic control operation in which the feedback voltage is regulated and tracks external input reference voltage. it also features complete fault protection functions including over voltage, under voltage and current limit. remote sense the rt8816a uses the remote sense path (vsns and rgnd) to overcome voltage drops in the power lines by sensing the voltage directly at the end of gpu. normally, to protect remote sense path disconnecting, there are two resistors (r local ) connecting between local sense path and remote sense path. that is, in application with remote sense, the r local is recommended to be 10 to 100 . if no need of remote sense, the r local is recommended to be 0 . out on ton in 2 v 3.2p t = r v0.5 ?? ? ? ? ? / sout inon f= v v t ? and then the switching frequency f s is : pwm operation the rt8816a integrates a constant-on-time (cot) pwm controller, and the controller provides the pwm signal which relies on the output ripple voltage comparing with internal reference voltage as shown in figure 4. referring to the function block diagram of ton genx, the synchronous ugate driver is turned on at the beginning of each cycle. after the internal one-shot timer expires, the ugate driver will be turned off. the pulse width of this one-shot is determined by the converter input voltage and the output voltage to keep the frequency fairly constant over the input voltage and output voltage range. another one-shot sets a minimum off-time. figure 3. output voltage sensing r ton is a resistor connected from the v in to ton pin. the recommend operation frequency range is 250khz to 750khz. on-time control the on-time one-shot comparator has two inputs. one input monitors the output voltage, while the other input samples the input voltage and converts it to a current. this input voltage proportional current is used to charge an internal on-time capacitor. the on-time is the time required for the voltage on this capacitor to charge from zero volts to v out , thereby making the on-time of the high- side switch directly proportional to output voltage and inversely proportional to input voltage. the implementation results in a nearly constant switching frequency without the need for a clock generator. figure 4. constant on-time pwm control v peak v out v valley t on v ref t v out 0 v out ugate lgate boot phase gpu - vsns gpu + v in rgnd r local + r local - local sense path remote sense path
rt8816a 13 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation phase number psi voltage setting 1phase with dem 0v to 0.4v 1phase with ccm 0.7v to 0.88v 2phase with dem 1.08v to 1.35v 2phase with ccm 1.6v to 5.5v table 1 active phase circuit setting the rt8816a operates as active phase being 2 phase, and 1 phase. when programming active phase being 1 phase, the ugate2, boot2, phase2, and lgate2 pins are floating. the active phase number can be programmed by psi pin voltage. refer to table 1 for detail mode selection the rt8816a can operate into 2 phases with force ccm, 1 phase with force ccm, 1 phase with dem and 2 phases with dem according to psi voltage setting. if psi voltage is pulled below 0.4v, the controller will operate into 1 phase with dem. in dem operation, the rt8816a automatically reduces the operation frequency at light load conditions for saving power loss. if psi voltage is pulled between 0.7v to 0.88v, the controller will switch operation into 1 phase with force ccm. if psi voltage is pulled between 1.08v to 1.35v, the controller will switch operation into 2 phase with dem. if psi voltage is pulled between 1.6v to 5.5v, the controller will switch operation into 2 phase with force ccm. the operation mode is summarized in table 1. moreover, the psi pin is valid after por of vr. diode-emulation mode in diode-emulation mode, the rt8816a automatically reduces switching frequency at light-load conditions to maintain high efficiency. as the output current decreases from heavy-load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. by emulating the behavior of diodes, the low side mosfet allows only partial of negative current when the inductor freewheeling current reaches negative value. as the load current is further decreased, it takes a longer figure 5. boundary condition of ccm/dem in out load(skip) on (v v ) it 2l ? ?? where t on is on-time. the switching waveforms may be noisy and asynchronous in light loading diode-emulation operation condition, but this is a normal operating condition that results in high light-load efficiency. trade-off in dem noise vs. light-load efficiency is made by varying the inductor value. generally, low inductor values produce a broad high efficiency range vs. load curve, while higher values result in higher full load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. the disadvantages for using higher inductor values include larger physical size and degraded load-transient response (especially at low input voltage levels). i peak i load = i peak/2 t on slope = (v in - v out ) / l t 0 i l time to discharge the output capacitor to the level that requires the next ? on ? cycle. in reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous conduction condition. the transition load point to the light load operation is shown in figure 5 and can be calculated as follows: forced-ccm mode the low noise, forced-ccm mode disables the zero- crossing comparator, which controls the low-side switch on-time. this causes the low-side gate drive waveform to be the complement of the high-side gate drive waveform. this in turn causes the inductor current to reverse at light loads as the pwm loop to maintain a duty ratio v out /v in . the benefit of forced-ccm mode is to keep the switching frequency fairly constant.
rt8816a 14 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 6. internal soft-start sequence enable and disable the en pin is a high impedance input that allows power sequencing between the controller bias voltage and another voltage rail. the rt8816a remains in shutdown if the en pin is lower than 550mv. when the en voltage rises above the 1.2v high level threshold, the rt8816a will begin a new initialization and soft-start cycle. power on reset (por), uvlo power on reset (por) occurs when v pvcc rises above to approximately 4.1v (typical), the rt8816a will reset the fault latch circuit and prepare for pwm operation. when the v pvcc is lower than 3.8v (typical), the under voltage lockout (uvlo) circuitry inhibits switching by keeping ugate and lgate low. soft-start the rt8816a provides internal soft-start function and external soft-start function. the soft-start function is used to prevent large inrush current and output voltage overshoot while the converter is being powered up. the soft-start function automatically begins once the chip is enabled. there is a delay time around 200us from en goes high to v out begins to ramp-up. if external capacitor from ocset/ss pin to gnd is removed, the internal soft-start function will be chosen. an internal current source charges the internal soft- start capacitor so that the internal soft-start voltage ramps up linearly. the output voltage will track the internal soft-start voltage during the soft-start interval. after the internal soft- start voltage exceeds the refin voltage, the output voltage no longer tracks the internal soft-start voltage but follows the refin voltage. therefore, the duty cycle of the ugate signal as well as the input current at power up are limited. the soft-start process is finished until the internal ssok go high and protection is not triggered. figure 6 shows the internal soft-start sequence. the rt8816a also provides a proximate external soft-start function, and the external soft-start sequence is shown in figure 7, an additional capacitor can be connected from ocset/ss pin to gnd. the external capacitor will be charged by internal current source to build soft-start voltage ramp. if external soft-start function is chosen, the external soft-start time should be set longer than internal soft-start time to avoid output voltage tracking the internal soft-start ramp, the external soft-start time setting is shown in figure 7, the recommend external soft-start slew rate is 0.1v/ms to 0.4v/ms. en internal ss lgate ugate pgood pvcc vout vrefin internal ssok normal soft-start soft discharged enable delay time en external ss lgate ugate pgood pvcc vout normal 120 % vrefin external ssok soft-start soft discharged enable delay time figure 7. external soft-start sequence
rt8816a 15 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 9. pwm vid analog circuit diagram power good output (pgood) the pgood pin is an open-drain output, and it requires a pull-up resistor. during soft-start, the pgood is held low and is allowed to be pulled high after v out achieved over uvp threshold and under ovp threshold. in additional, if any protection is triggered during operation, the pgood will be pulled low immediately. pwm vid and dynamic output voltage control the rt8816a features a pwm vid input for dynamic output voltage control as shown in figure 9, which reduces the number of device pin and enables a wide dynamic voltage range. the output voltage is determined by the applied voltage on the refin pin. the pwm duty cycle determines the variable output voltage at refin. the soft-start time can be calculated as: ss refin ss ss (c x v ) t= i where i ss = 50 a (typ.), v refin is the voltage of refin pin, and c ss is the external capacitor placed from ocset/ ss pin to gnd. v out ss t ss v refin ocset/ss i ss c ss vcc figure 8. external soft-start time setting rgnd refin refadj vref vid pwm in q1 c refin r ref2 r boot r ref1 r refadj r standby standby mode control buffer rgnd rgnd rgnd rgnd c refadj with the external circuit and vid control signal, the controller provides three operation modes shown as figure 10. vref pwm vid refin boot mode normal mode boot mode standby mode standby control figure 10. pwm vid time diagram boot mode vid is not driven, and the buffer output is tri-state. at this time, turn off the switch q1 and connect a resistor divider as shown in figure 9 that can set the refin voltage to be v boot as the following equation : ?? ? ?? ?? ?? ref2 boot vref ref1 ref2 boot r v = v rr r ? ?? standby vref ref2 standby ref1 boot ref2 standby v = v r// r r r (r // r ) standby mode an external control can provide a very low voltage to meet v out operating in standby mode. if the vid pin is floating and switch q1 is enabled as shown in figure 9, the refin pin can be set for standby voltage according to the calculation below : where v vref = 2v (typ.) choose r ref2 to be approximately 10k , and the r ref1 and r boot can be calculated by the following equations : ?? ?? ?? ref2 vref boot ref1 boot boot ref2 vref boot ref1 boot boot ref2 vref boot boot ref1 boot rvv rr v rvv rr v rvv rr v ?? ?? ?? ?? ?? ?? by choosing r ref1 , r ref2 , and r boot , the r standby can be calculated by the following equation :
rt8816a 16 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ?? ? ? ? ? ?? ref2 min vref ref2 boot refadj boot ref2 ref1 refadj boot ref2 r v = v rr r // (r r ) r r // (r r ) ? ?? ref2 max vref ref1 refadj boot ref2 r v = v (r // r ) r r ? max min step max (v v ) v = n normal mode if the vid pin is driven by a pwm signal and switch q1 is disabled as shown in figure 9, the v refin can be adjusted from v min to v max , where v min is the voltage at zero percent pwm duty cycle and v max is the voltage at one hundred percent pwm duty cycle. the v min and v max can be set by the following equations : the relationship between vid duty and v refin is shown in figure 10, and v out can be set according to the calculation below : ?? out min step v = v nv where v step is the resolution of each voltage step 1 : where nmax is the number of total available voltage steps and n is the number of step at a specific v out . the dynamic voltage vid period (t vid = t u x n max ) is determined by the unit pulse width (t u ) and the available step number (n max ). the recommended t u is 27ns. ?? ?? standby ref2 ref1 boot standby ref2 ref standby ref1 ref2 boot ref1 r rrr v rvv rrr r ? ?? ? ?? ? ? ? ? by choosing r ref1 , r ref2 , and r boot , the r refadj can be calculated by the following equation : ref1 min refadj max min rv r vv ? ? ? vid slew rate control in rt8816a , the v refin slew rate is proportional to pwm vid duty, the rising time and falling time are the same. in normal mode, the v refin slew rate sr can be estimated by c refadj or c refin as the following equation : when choose c refadj : ?? ?? ?? ? ?? refin_final refin_initial sr refin sr ref1 refadj boot ref2 (v v ) 80% sr = 2.2r c r = r // r r // r current limit the rt8816a provides cycle-by-cycle current limit control by detecting the phase voltage drop across the low-side mosfet when it is turned on. the current limit circuit employs a unique ? valley ? current sensing algorithm as shown in figure 12. if the magnitude of the current sense signal at phase is above the current limit threshold, the pwm is not allowed to initiate a new cycle. in order to provide both good accuracy and a cost effective solution, the rt8816a supports temperature compensated mosfet r ds(on) sensing. when choose c refin : ?? refin_final refin_initial sr refadj sr ref1 refadj boot ref2 (v v ) 80% sr = 2.2r c r = (r // r ) // (r +r ) ?? the recommend sr is estimated by c refadj . figure 11. pwm vid analog output v min v max n = 1 n = 2 t u n = 1 n = 2 n = n max t vid = n max x t u v refin vid duty 0 0.5 1 vid input vid input
rt8816a 17 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. negative current limit the rt8816a supports cycle-by-cycle negative current limit. the absolute value of negative current limit threshold is the same with the positive current limit threshold. if negative inductor current is rising to trigger negative current limit, the low-side mosfet will be turned off and the current will flow to input side through the body diode of the high-side mosfet. at this time, output voltage tends to rise because this protection limits current to discharge the output capacitor. in order to prevent shutdown because of over-voltage protection, the low-side mosfet is turned on again 400ns after it is turned off. if the device hits the negative current limit threshold again before output voltage is discharged to the target level, the low-side mosfet is turned off and process repeats. it ensures maximum allowable discharge capability when output voltage continues to rise. on the other hand, if the output is discharged to the target level before negative current limit threshold is reached, the low-side mosfet is turned off, the high- side mosfet is then turned on, and the device keeps normal operation. current balance the rt8816a implements current balance mechanism in the current loop. the rt8816a senses per phase current signal and compares it with the average current. if the sensed current of any particular phase is higher than the average current, the on-time of this phase will be decreased. the current balance accuracy is major related with on- resistance of low-side mosfet (r lg,ds(on) ). that is, in practical application, using lower r lg,ds(on) will reduce the current balance accuracy. output over-voltage protection (ovp) the output voltage can be continuously monitored for over- voltage protection. if refin voltage is lower than 1.33v, the over voltage threshold follows to absolute over voltage 2v. if refin voltage is higher than 1.33v, the over voltage threshold follows relative over voltage 1.5 x v refin . when ovp is triggered, ugate goes low and lgate is forced figure 12. ? valley ? current limit where i valley represents the desired pre-phase inductor limit current (valley inductor current) and i ocset is current limit setting current which has a temperature coefficient to compensate the temperature dependency of the r ds(on) . during soft-start period (en is pulled high to ssok), the i ocset is 50 a. once soft-start complete, the i ocset will switch to 10 a. for ensure the soft-start and current limit function works normally. below setting limitation must be followed. r ocset x 50 a > 1.2 x v refin if r ocset is not present, there is no current path for i ocset to build the current limit threshold. in this situation, the current limit threshold is internally preset to 200mv. i l,peak i load i l,valley t 0 i l in an over-current condition, the current to the load exceeds the average output inductor current. thus, the output voltage falls and eventually crosses the under-voltage protection threshold, inducing ic shutdown. current limit setting rt8816a adopts per-phase current limiting protection. the current limit threshold can be set by a resistor (r ocset ) between ocset/ss pin and gnd. once pvcc exceeds the por threshold and chip is enabled, an internal current source i ocset flows through r ocset . the voltage across r ocset is stored as the current limit protection threshold v ocset . the threshold range of v ocset is 30mv to 200mv. it can be calculated according to the following equation: ocset ocset ocset i x r v = 12 r ocset can be determined using the following equation : valley ds_on ocset ocset i x r x 12 r = i
rt8816a 18 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. high. the rt8816a is latched once ovp is triggered and can only be released by pvcc or en power on reset. a 5 s delay is used in ovp detection circuit to prevent false trigger. output under-voltage protection (uvp) the output voltage can be continuously monitored for under- voltage protection. when the output voltage is less than 40% of its set voltage, under voltage protection is triggered and then all ugate and lgate gate drivers are forced low. there is a 3 s delay built in the uvp circuit to prevent false transitions. during soft-start, the uvp blanking time is equal to pgood blanking time. mosfet gate driver the rt8816a integrates high current gate drivers for the mosfets to obtain high efficiency power conversion in synchronous buck topology. a dead-time is used to prevent the crossover conduction for high-side and low-side mosfets. because both the two gate signals are off during the dead-time, the inductor current freewheels through the body diode of the low-side mosfet. the freewheeling current and the forward voltage of the body diode contribute power losses to the converter. the rt8816a employs adaptive dead time control scheme to ensure safe operation without sacrificing efficiency. furthermore, elaborate logic circuit is implemented to prevent cross conduction. for high output current applications, two power mosfets are usually paralleled to reduce r ds(on) . the gate driver needs to provide more current to switch on/off these paralleled mosfets. gate driver with lower source/sink current capability results in longer rising/falling time in gate signals and higher switching loss. the rt8816a embeds high current gate drivers to obtain high efficiency power conversion. mosfet selection the majority of power loss in the step-down power conversion is due to the loss in the power mosfets. for low voltage high current applications, the duty cycle of the high-side mosfet is small. therefore, the switching loss of the high-side mosfet is of concern. power mosfets with lower total gate charge are preferred in such kind of application. however, the small duty cycle means the low-side mosfet is on for most of the switching cycle. therefore, the conduction loss tends to dominate the total power loss of the converter. to improve the overall efficiency, the mosfets with low r ds(on) are preferred in the circuit design. in some cases, more than one mosfet are connected in parallel to further decrease the on-state resistance. however, this depends on the low-side mosfet driver capability and the budget. inductor selection inductor plays an importance role in step-down converters because the energy from the input power rail is stored in it and then released to the load. from the viewpoint of efficiency, the dc resistance (dcr) of inductor should be as small as possible to minimize the copper loss. in additional, the inductor occupies most of the board space so the size of it is important. low profile inductors can save board space especially when the height is limited. however, low dcr and low profile inductors are usually not cost effective. additionally, higher inductance results in lower ripple current, which means the lower power loss. however, the inductor current rising time increases with inductance value. this means the transient response will be slower. therefore, the inductor design is a trade-off between performance, size and cost. in general, inductance is designed to let the ripple current ranges between 20% to 40% of full load current. the inductance can be calculated using the following equation : ? ? ?? in out out min sw out_rated in vv v l = fki v where k is the ratio between inductor ripple current and rated output current. input capacitor selection voltage rating and current rating are the key parameters in selecting input capacitor. generally, input capacitor has a voltage rating 1.5 times greater than the maximum input voltage is a conservatively safe design. the input capacitor is used to supply the input rms current, which can be approximately calculated using the
rt8816a 19 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. following equation : out out rms out in in vv i = i 1 vv ?? ??? ?? ?? the next step is to select proper capacitor for rms current rating. use more than one capacitor with low equivalent series resistance (esr) in parallel to form a capacitor bank is a good design. besides, placing ceramic capacitor close to the drain of the high-side mosfet is helpful in reducing the input voltage ripple at heavy load. output capacitor selection the output filter capacitor must have esr low enough to meet output ripple and load transient requirement, yet have high enough esr to satisfy stability requirements. also, the capacitance must be high enough to absorb the inductor energy going from a full load to no load condition without tripping the ovp circuit. organic semiconductor capacitor(s) or special polymer capacitor(s) are recommended. mosfet selection the majority of power loss in the step-down power conversion is due to the loss in the power mosfets. for low voltage high current applications, the duty cycle of the high-side mosfet is small. therefore, the switching loss of the high-side mosfet is of concern. power mosfets with lower total gate charge are preferred in such kind of application. however, the small duty cycle means the low-side mosfet is on for most of the switching cycle. therefore, the conduction loss tends to dominate the total power loss of the converter. to improve the overall efficiency, the mosfets with low r ds(on) are preferred in the circuit design. in some cases, more than one mosfet are connected in parallel to further decrease the on-state resistance. however, this depends on the low-side mosfet driver capability and the budget. thermal considerations the junction temperature should never exceed the absolute maximum junction temperature t j(max) , listed under absolute maximum ratings, to avoid permanent damage to the device. the maximum allowable power figure 13. derating curve of maximum power dissipation 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0255075100125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb dissipation depends on the thermal resistance of the ic package, the pcb layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. the maximum power dissipation can be calculated using the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction-to-ambient thermal resistance. for continuous operation, the maximum operating junction temperature indicated under recommended operating conditions is 125 c. the junction-to-ambient thermal resistance, ja , is highly package dependent. for a wqfn-20l 3x3 package, the thermal resistance, ja , is 30 c/w on a standard jedec 51-7 high effective-thermal- conductivity four-layer test board. the maximum power dissipation at t a = 25 c can be calculated as below : p d(max) = (125 c ? 25 c) / (30 c/w) = 3.33w for a wqfn-20l 3x3 package the maximum power dissipation depends on the operating ambient temperature for the fixed t j(max) and the thermal resistance, ja . the derating curves in figure 13 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
rt8816a 20 DS8816A-00 september 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout considerations layout is very important in high frequency switching converter design. if designed improperly, the pcb could radiate excessive noise and contribute to the converter instability. following layout guidelines must be considered before starting a layout for rt8816a. ? place the rc filter as close as possible to the pvcc pin. ? keep current limit setting network as close as possible to the ic. routing of the network should avoid coupling to high voltage switching node. ? connections from the drivers to the respective gate of the high-side or the low-side mosfet should be as short as possible to reduce stray inductance. ? all sensitive analog traces and components such as vsns, rgnd, en, psi, vid, pgood, vref, ton vrefadj, vrefin and tsns should be placed away from high voltage switching nodes such as phase, lgate, ugate, or boot nodes to avoid coupling. use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. ? power sections should connect directly to ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). power components should be placed to minimize loops and reduce losses.
rt8816a 21 DS8816A-00 september 2016 www.richtek.com richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 2.900 3.100 0.114 0.122 d2 1.650 1.750 0.065 0.069 e 2.900 3.100 0.114 0.122 e2 1.650 1.750 0.065 0.069 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 20l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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